Embedded electrical interconnects within dielectric substrates find widespread use for various electronic applications. For example, microprocessor integrated circuits generally include numerous levels of interconnect routing in the form of electrical interconnects, such as lines and dots, embedded within a dielectric substrate to connect transistors within the integrated circuits. Each level of interconnect routing is separated from immediately adjacent levels by the dielectric material, referred to in the art as an interlayer dielectric (ILD). The ILD generally includes an oxide layer that includes an oxide, such as silicon dioxide formed from tetraethyl orthosilicate (TEOS), and may include one or more additional layers of dielectric material such as low-k or ultra-low k (ULK) material. Adjacent levels of interconnect routing may be embedded in distinct layers of ILD, and with the interconnect routing configured in such a way so as to ensure that dielectric material separates the adjacent interconnect routings. In this regard, the embedded electrical interconnects in the interconnect routing can be selectively insulated from both other embedded electrical interconnects in the same interconnect routing and from embedded electrical interconnects in interconnect routing of adjacent levels. Likewise, embedded electrical interconnects in adjacent levels of interconnect routing can also be selectively connected to fabricate desired circuitry in the integrated circuits.
To form levels of interconnect routing, the ILD is generally formed followed by selective etching of recesses, such as trenches or vias, in the ILD. Metal interconnects are then formed through blanket deposition of metal over the ILD and in the recesses, followed by chemical-mechanical planarization (CMP). Under some circumstances, additional processing is conducted after recess formation and prior to formation of the metal interconnects, and the additional processing may degrade the ILD and cause damage to the integrated circuit. For example, in some circumstances, an ILD is formed directly over embedded electrical contacts in a base substrate, followed by recess formation to expose the embedded electrical contacts. “Base substrate”, as referred to herein, includes any underlying substrate (including a semiconductor substrate or a dielectric substrate) that have an embedded electrical contact therein (such as a source/drain region for a transistor or an electrical interconnect). Metal interconnects are subsequently formed in the recesses and are electrically connected to the embedded electrical contacts through the ILD. The embedded electrical contacts include silicon-containing material, which may have an undesirably high contact resistance. To lower contact resistance between the embedded electrical contacts and the subsequently-formed metal interconnects, a metal silicide layer may be formed in the embedded electrical contact by blanket depositing a thin layer of silicide-forming metal on the ILD and the embedded electrical contact in the recess followed by annealing to form the metal silicide layer. Unreacted silicide-forming metal is then removed such as by wet etching in a H2O2/H2SO4 or HNO3/HCL solution. The ILD is vulnerable to damage at various points during silicide formation. Furthermore, the ILD that is formed directly over the embedded electrical contacts may have interfaces between various layers in the ILD, and damage to the interfaces in the recesses can result in flow of metal ions from the metal interconnect or other harsh compounds through the interfaces to other sensitive features within the integrated circuit. Further still, time dependent dielectric breakdown (TDDB), which results from migration of metal ions from the embedded electrical interconnects into an interface between adjacent levels of ILD, is a concern for layers of ILD that are spaced from the embedded electrical contacts. While it is generally known to form an electrically-conductive barrier layer in recesses prior to forming metal interconnects, the electrically-conductive barrier layers are formed just prior to metal interconnect formation and effectively seal the metal interconnect from the remaining exposed portions of the ILD. Therefore, formation of the electrically-conductive barrier layer is often too late to protect the ILD from the additional processing, which may degrade the ILD and cause damage to the integrated circuit.
Accordingly, it is desirable to provide methods of forming integrated circuits having an embedded electrical interconnect within an interlayer dielectric with the interlayer dielectric protected from damage that may occur after recess formation but prior to formation of the embedded electrical interconnect and any other electrically-conductive features in the recess. In addition, it is desirable to provide integrated circuits having a substrate with an embedded electrical interconnect disposed therein, with a protecting liner disposed between the interlayer dielectric and the embedded electrical interconnect, while still enabling electrical connection to be established between the embedded electrical contact in the base substrate and the embedded electrical interconnect in the ILD. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.